As is known, computers are capable of performing a wide variety of tasks ranging from simple tasks to very involved tasks. However, some tasks cannot be executed efficiently, since they are too large to be held in memory, run too slow on one processor or require too many resources. These tasks are referred to as complex tasks. One example of a complex task is a static timing analysis of a logic design.
During static timing analysis, a new design is timed to determine if it meets predetermined specifications. The design includes thousands of logic circuits and many interconnection paths between the circuits. As is known, the output of one circuit may be an input to another circuit. Since the timing value of one circuit is needed before timing can be calculated for a connected circuit, static timing has traditionally been performed serially. This disadvantageously takes a great deal of time and resources.
Previously, efforts have been made to improve the overall processing time of a design such that the design meets the predetermined specification. For instance, in U.S. Pat. No. 4,698,760, entitled "Method Of Optimizing Signal Timing Delays and Power Consumption in LSI Circuits," issued on Oct. 6, 1987, a method is described for optimizing signal timing delays through LSI circuits by proper selection of circuit power levels. Power levels for individual logic blocks are selected such that overall system timing requirements are met.
However, the problem associated with improving the performance of timing a design to determine if it meets the predefined specifications has not been adequately dealt with. Therefore, a need exists for a technique to increase the performance associated with execution of complex tasks, and in particular, the performance associated with static timing. A further need exists for a technique to incrementally substitute part of the design when the design does not adequately meet the specification or the designer wishes to change the design.